1. Field of the Invention
The present invention relates to a semiconductor device comprising an MOS transistor formed on an SOI (silicon(semiconductor)-on-insulator) substrate and, in particular, to its I/O protection function.
2. Description of the Background Art
In MOS transistors formed on SOI substrates in which a silicon thin film is formed on an insulating substrate (referred to as xe2x80x9cSOI devicexe2x80x9d in some cases), its source and drain regions reach the insulating substrate so that each junction capacity is reduced, permitting high speed and low dissipation power operation.
Specifically, in MOS transistors formed on normal bulk silicon substrates (referring to as xe2x80x9csubstrate devicexe2x80x9d in some cases), the respective junction capacity of drain and source regions is increased at low voltages and its performance (particularly, operation speed) is extremely lowered. On the other hand, since SOI devices have less components for the respective junction capacity of drain and source regions, so that they have little performance degradation, permitting high speed and low dissipation power operation.
As described, since SOI devices provide high speed and low dissipation power operation, they are highly anticipated to be utilized as devices for portable apparatuses.
Although SOI devices are expected to be used as devices for low-voltage operation, they have poor ESD (Electro Static Discharge) resistance in I/O protection circuits. The reason for being called I/O protection circuit is that a surge voltage can be applied from output terminals as well as input terminals.
FIG. 23 is a sectional view of an SOI structure. As shown in the figure, a buried oxide film 2 is formed on a semiconductor substrate 1, and an SOI layer 3 is formed on the oxide film 2. The structure comprising the semiconductor substrate 1, the buried oxide film 2, and the SOI layer 3, is called SOI substrate. A gate oxide film 4 is selectively formed on the SOI layer 3, and a gate electrode 5 is formed on the gate oxide film 4. The SOI layer 3 underlying the gate oxide film 4 serves as a channel region 8, and regions of the SOI layer 3 adjacent to the channel region 8 serve as a drain region 6 and a source region 7.
In the above SOI structure, heat generated when applied a surge voltage is accumulated by the presence of the buried oxide film 2 whose thermal conductivity is poor (about one-tenth of that of silicon). It is therefore liable to cause a thermal runaway or 2nd breakdown, resulting in permanent breakage of semiconductor devices on SOI substrates.
FIG. 24 is a graph diagram showing a process of a thermal runaway. This figure shows a process of a thermal runaway at the time of reverse bias connection, e.g., when an input voltage (surge voltage SV) is applied to a drain of an NMOS transistor Q1 whose source and gate are grounded as shown in FIG. 25. The thermal runaway process of FIG. 24 comprises subprocesses P1 to P5.
When a surge voltage SV far beyond ordinary ones is applied to the drain of the NMOS transistor Q1 in FIG. 25, its drain voltage rises rapidly (P1) and reaches a breakdown induced voltage. Then, the transistor Q1 causes an avalanche breakdown so that the current begins to flow, lowering to a holding voltage temporarily (P2). Thereafter, it starts to rise again (P3) and, when it reaches a thermal breakdown voltage, portions of the transistor Q1 become a melted state so that the resistance value between the source and drain is rapidly lowered, causing a rapid voltage drop (P4). The flow of current concentrates on the transistor Q1 that has caused such a rapid drop of resistance value between the source and drain, that is, a positive feedback is effected (P5). As a result, the transistor Q1 is completely broken. For instance, as shown in FIG. 26, a large defect 10 due to the thermal breakdown occurs in the gate electrode 5, thereby making the transistor operation impossible.
Generally, in cases where, as an I/O protection circuit on an SOI substrate, NMOS transistors are provided by a reverse bias, NMOS transistors having a channel width W are connected in parallel between an input (voltage) IN and a ground level as shown in FIG. 27. In the case of FIG. 27, six NMOS transistors T1 to T6 whose gate is grounded are provided in parallel between an input IN and a ground level as shown in FIG. 28. The NMOS transistor T1 comprises a gate electrode 51, a drain region 61, and a source region 71. The NMOS transistor T2 comprises a gate electrode 52, a drain region 61, and a source region 72. The NMOS transistor T3 comprises a gate electrode 53, a drain region 62, and a source region 72. The NMOS transistor T4 comprises a gate electrode 54, a drain region 62, and a source region 73. The NMOS transistor T5 comprises a gate electrode 55, a drain region 63, and a source region 73. The NMOS transistor T6 comprises a gate electrode 56, a drain region 63, and a source region 74. The input voltage IN as a surge voltage is input from an external input terminal or an external output terminal.
Providing the six NMOS transistors T1 to T6 in parallel between the input IN and the ground level as an I/O protection circuit on an SOI substrate, enables to distribute the current into the transistors T1 to T6 when the current flows between the input IN and the ground level.
If, however, one of the NMOS transistors T1 to T6 causes an avalanche breakdown and reaches a thermal breakdown voltage, a resistance value between the source and drain of such a transistor is rapidly lowered. As shown in a subprocess P5 in FIG. 24, the flow of current concentrates on such a transistor that has reached a thermal breakdown voltage, failing to suppress this transistor from being broken.
Thus, with the I/O protection circuit utilizing the NMOS transistors of the conventional SOI structure, even if, in order to improve a surge resistance, a plurality of NMOS transistors in parallel connection constitute an I/O protection circuit as shown in FIG. 27, expected improvement in ESD resistance cannot be accomplished.
According to a first aspect of the present invention, a semiconductor device formed on an SOI substrate has an I/O protection circuit portion including at least one first MOS transistor connected to an external terminal by a forward bias, and a plurality of second MOS transistors connected in parallel to the external terminal by a reverse bias. In this semiconductor device, a resistance value of each drain resistance of the plurality of second MOS transistors is set so that an ESD (Electro Static Discharge ) resistance of the plurality of second MOS transistors is approximately equal to or greater than that of the at least one first MOS transistor.
According to a second aspect of the invention, the semiconductor device of the first aspect further comprises an internal circuit portion that performs signal processing based on signals from the external terminal. In this semiconductor device, the internal circuit includes an MOS transistor for internal circuit having a conductivity type identical with that of the plurality of second MOS transistors, and the MOS transistor for internal circuit has a drain resistance whose resistance value is smaller than that of each drain resistance of the plurality of second MOS transistors.
According to a third aspect of the invention, in the semiconductor device of the second aspect, a plurality of first silicide layers are respectively provided on drain regions of the plurality of second MOS transistors, a second silicide layer is provided on a drain region of the MOS transistor for internal circuit, and the first silicide layer is thinner in thickness than the second silicide layer.
According to a fourth aspect of the invention, in the semiconductor device of the first aspect, the conductivity type of the at least one first MOS transistor and the-plurality of second MOS transistors is n-type.
According to a fifth aspect of the invention, in the semiconductor device of the fourth aspect, each resistance value of the plurality of second MOS transistors is not less than 30 xcexa9 per 1 xcexcm of channel width.
According to a sixth aspect of the invention, a semiconductor device formed on an SOI substrate has an I/O protection circuit portion connecting an MOS transistor for I/O protection to an external terminal, and an internal circuit comprising an MOS transistor for internal circuit to perform a prescribed signal processing therein. In this semiconductor device, a drain region of the MOS transistor for I/O protection has first regions upon which no silicide layer is formed, and a second region upon which a silicide layer is formed and a drain region of the MOS transistor for internal circuit has a third region upon which a silicide layer is formed; the first regions being higher in impurity concentration than the third region.
According to a seventh aspect of the invention, the semiconductor device of the sixth aspect is characterized in that the second region is lower in impurity concentration than the first regions.
According to an eighth aspect of the invention, a semiconductor device formed on an SOI substrate has an I/O protection circuit portion connecting a PMOS transistor for I/O protection to an external terminal. In this semiconductor device, the channel region property of said PMOS transistor is set to improve an ESD resistance of the PMOS transistor without affecting an integration degree.
According to a ninth aspect of the invention, the semiconductor device of the eighth aspect is characterized in that the I/O protection circuit portion further includes an NMOS transistor for I/O protection, and a channel length of the PMOS transistor for I/O protection is shorter than a channel length of the NMOS transistor for I/O protection.
According to a tenth aspect of the invention, the semiconductor device of the eighth aspect further comprises an internal circuit portion including a PMOS transistor for internal circuit to perform signal processing therein. In this semiconductor device, portions adjacent to a channel region in a drain region of the PMOS transistor for I/O protection is higher in impurity concentration than portions adjacent to a channel region in a drain region of the PMOS transistor for internal circuit.
According to an eleventh aspect of the invention, the semiconductor device of the eight aspect further comprises an internal circuit portion having a PMOS transistor for internal circuit to perform signal processing therein. In this semiconductor device, the PMOS transistor for I/O protection is shorter in channel length than the PMOS transistor for internal circuit.
According to a twelfth aspect of the invention, a semiconductor device formed on an SOI substrate has an I/O protection circuit corresponding to an external terminal. The I/O protection circuit has only NMOS transistors connected between a power supply and a ground level.
According to a thirteenth aspect of the invention, a semiconductor device formed on an SOI substrate has an I/O protection circuit corresponding to an external terminal, and further includes a power supply wire connected to a power supply in common and a ground wire connected to a ground level in common. In this semiconductor device, the I/O protection circuit includes an NMOS transistor in a diode connection between the power supply wire and the ground wire, and an MOS transistor for I/O protection provided between the external terminal and at least one of the power supply wire and the ground wire.
According to a fourteenth aspect of the invention, the semiconductor device of the thirteenth aspect further comprises a capacitor provided between the power supply wire and the ground wire of the I/O protection circuit portion.
In the semiconductor device of the first aspect, in order that the ESD resistance due to a plurality of second MOS transistors connected by a reverse bias is approximately equal to or greater than the ESD resistance due to at least one of first MOS transistors connected by a forward bias, the resistance value of drain resistance of the second MOS transistors is set respectively. It is therefore possible to obtain I/O protection circuits that exhibit excellent ESD resistance in both forward and reverse connections of the MOS transistors.
In the semiconductor device of the second aspect, the MOS transistor for internal circuit has a smaller resistance value of drain resistance than each drain resistance of the plurality of second MOS transistors. This prevents the drive capability of the MOS transistor for internal circuit from lowering than necessary.
In the semiconductor device of the third aspect, by decreasing the film thickness of a plurality of first silicide layers in the MOS transistor for I/O protection than that of the second silicide layer in the MOS transistor for internal circuit, the drain resistance of the MOS transistor for I/O protection can be increased than that of the MOS transistor for internal circuit. It is therefore possible to increase the resistance value of drain resistance due to the second MOS transistors in the I/O protection circuit so as to have an ESD resistance approximately equal to that due to at least one fist MOS transistor, and also to decrease the resistance value of drain resistance of the MOS transistor for internal circuit so as to obtain a desired drive capability.
In the semiconductor device of the fourth aspect, the conductivity type of at least one first MOS transistor and a plurality of second MOS transistors is n-type. NMOS transistors produce a snap back phenomenon that at the time of reverse bias connection, its drain voltage reaches a breakdown induced voltage to cause an avalanche breakdown so that the resistance value between the source and drain is lowered and the drain voltage is then lowered. This results in the problem that the flow of current concentrates on an NMOS transistor that has caused an avalanche breakdown for the first time to reduce the resistance value between the source and drain, leading to a thermal breakdown. However, by increasing the each resistance value of drain resistance of the plurality of second MOS transistor so as to have an ESD resistance approximately equal to that of at least one first MOS transistor, it is possible to suppress a reduction in resistance value between the source and drain because of the snap back phenomenon, thereby avoiding the above problem.
In the semiconductor device of the fifth aspect, by setting each resistance value of a plurality of second NMOS transistor per 1 xcexcm of channel width to 30 xcexa9 or more, it is possible to obtain an ESD resistance approximately equal to that of at least one first MOS transistor connected by a forward bias.
In the semiconductor device of the sixth aspect, the impurity concentration of the first region upon which no silicide layer is formed in the MOS transistor for I/O protection, is higher than that of the third region upon which the silicide layer is formed in the MOS transistor for internal circuit. By decreasing the resistance value of the first region, transistors for I/O protection circuit having a high drive capability can be obtained.
In the semiconductor device of the seventh aspect, the impurity concentration of a second region upon which the silicide layer is formed in the MOS transistor for I/O protection, is lower than that of the first region upon which no silicdie layer is formed, thus exerting no harmful effect on the silicide layer formed in the first region, irrespective of the impurity concentration of the second region.
In the semiconductor device of the eighth aspect, the channel region property of the PMOS transistor is set to improve the ESD resistance without affecting the integration degree of the PMOS transistors for I/O protection. This enables to improve the ESD resistance of PMOS transistors that are generally inferior to NMOS transistors in ESD resistance, thus reducing a difference in ESD resistance between the PMOS transistors for I/O protection and the NMOS transistors for I/O protection. This permits the I/O protection circuits whose ESD resistance does not deteriorate even if PMOS transistors are used.
In the semiconductor device of the ninth aspect, the channel length of the PMOS transistor for I/O protection is shorter than that of the NMOS transistor for I/O protection. This enables to lower the breakdown induced voltage so that the ESD resistance is improved without affecting the integration degree.
In the semiconductor device of the tenth aspect, the impurity concentration of portions adjacent to the channel region in the drain region of the PMOS transistor for I/O protection is higher than that of portions adjacent to the channel region in the drain region of the PMOS transistor for internal circuit. This enables to lower the breakdown induced voltage so that the ESD resistance is improved without affecting the integration degree.
In the semiconductor device of the eleventh aspect, the channel length of the PMOS transistor for internal circuit is shorter than that of the PMOS transistor for I/O protection. This enables to lower the breakdown induced voltage so that the ESD resistance is improved without affecting the integration degree.
In the I/O protection circuit of the semiconductor device of the twelfth aspect, only the NMOS transistors are connected between a power supply and a ground level. Since the NMOS transistors are superior to the PMOS transistors in ESD resistance, it is possible to obtain I/O protection circuits excellent in ESD resistance.
The I/O protection circuit of the semiconductor device of the thirteenth aspect includes the NMOS transistor provided between the power supply wire and the ground wire by a diode connection, and the MOS transistor for I/O protection circuit provided between the external terminal and at least either of the power supply wire and the ground wire. Therefore, when a surge voltage is applied to the external terminal, the discharge current flows through a current path connected between the external terminal, the MOS transistor for I/O protection, one of the power supply wire and the ground wire connected the MOS transistor for I/O protection, the NMOS transistor and the other of the power supply wire and the ground wire. As a result, the surge voltage is always discharged through the NMOS transistor excellent in ESD resistance, making it possible to obtain I/O protection circuits excellent in ESD resistance on SOI substrates.
In the semiconductor device of the fourteenth aspect, the capacitor is added between the power supply and the ground level in the I/O protection circuit. Therefore, a surge voltage can be charged by the capacitor, thereby dispersing the surge voltage.
An object of the present invention is to provide a semiconductor device of SOI structure with improved ESD resistance.
These and other object, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.